Write a verilog code for a FIFO….. it can be done in behavioral modeling without much hassle. First In First Out memory has given size (in my case its 16 bit 16 registers) it has internal read and write pointers and external read & Write enable signal. once you write it and it will get written into memory and write pointer will get incremented. similarly for the read pointer. and there will be two signals Full and Empty which will show that the status of the FIFO. and all this will be synchronized with a clock.
Now a problem is can there be both Read and write operation at the same time. Of course we can’t perform the read and write operation simultaneously at same location. But by reasoning we can show that when read and write pointer will point same location it will be either empty or full. so we can check for that condition.
Now suppose that FIFO is empty. both read and write signal is enable. and we’re giving data at the input of the FIFO. What will happen??
- Is it possible to make both enable at same time??
- Does FIFO becomes transparent at that time?
- which operation will get the priority write or read??
I’ve submitted the code for FIFO but still i don’t have the answer for this question. anybody can help??
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